• "Some physicists predicted that within the next 10 to 20 years quantum computers will be built that are sufficiently powerful to implement Shor’s ideas and to break all existing public key schemes. Thus we need to look ahead to a future of quantum computers, and we need to prepare the cryptographic world for that future.”

    Prof Seth Lloyd of MIT, MIT Review 2008

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  • “Build-in Security: Ensure that security is considered and built into the design of new infrastructure, so that our critical assets are protected from the start and more resilient to naturally-occurring and deliberate threats throughout their life-cycle."

    Obama-Biden Plan, Agenda: Homeland Security, December 2008

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  • "Even a relatively small quantum computer, one that had a few tens of thousands of qubits, could consider so many different values at once that it would be able to break all known [ed: RSA, D&H, ECC, AES-128] codes commonly used for secure Internet communication.”

    Prof Seth Lloyd of MIT, MIT Review 2008

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Home Resources Synaptic publications Cryptographic white papers: VEST pub: 20 Gb/s VEST-32 on 110nm LSI Rapidchip (2006)
pub: 20 Gb/s VEST-32 on 110nm LSI Rapidchip (2006)
Wednesday, 01 February 2006 00:00
Authors:

Benjamin Gittins
Organisation:

Synaptic Laboratories Limited
Date:

February, 2006
Keywords: VEST, ASIC
Electronic Publication: Short Paper in PDF | Long Paper in PDF
Abstract:

This paper is a preliminary report on the static-timing, R-Cell, die-area and staticpower requirements of the complete data-path of VEST-32 ciphers on LSI Logic RapidChip 180ηm and 110ηm Technologies. Based on the conservative standard RapidChip design front-end sign-off process, VEST-32 can effortlessly satisfy a demand for 256-bit secure 10 Gb/s authenticated encryption @ 167 MHz on 180ηm LSI Logic RapidChip platform ASIC technologies in less than 45K Gates and zero SRAM. On the 110ηm Rapidchip technologies, VEST-32 offers 20 Gb/s authenticated encryption @ 320 MHz in less than 45 K gates. Similar bandwidth performance may be achievable with reduced circuit area using a custom sign-off process.
Quote:
See:
Citation:

Benjamin Gittins, "VEST-32, 256-bit secure, Single-Pass Authenticated Encryption, 20 Gigabit/s @ 312MHz on 110ηm LSI Logic RapidChip Platform ASIC Technology in <45K Gates, Zero SRAM and <150mW", Synaptic Laboratories Limited, February 2006
Related work:

pub: VEST, AES, SHA Hardware Performance Survey (2005)


Last Updated on Sunday, 23 October 2011 09:00