Home Resources Synaptic publications Cryptographic white papers: VEST pub: VEST, AES, SHA Hardware Performance Survey (2005)
pub: VEST, AES, SHA Hardware Performance Survey (2005)
Tuesday, 01 November 2005 00:00
Full Title: A Presentation on VEST Hardware Performance, Chip Area Measurements, Power Consumption Estimates and Benchmarking in Relation to the AES, SHA-256 and SHA-512
Authors:

Benjamin Gittins, Howard A. Landman, Sean O'Neil and Ron Kelson
Organisation:

Synaptic Laboratories Limited
Date:

Nov, 2005
Keywords: implementation, stream ciphers, hash functions, authenticated encryption, message digest, message authentication code, fastest hardware cipher, AES, SHA-256, SHA-512, SHA-2, FPGA, ASIC
Pages: 42
Electronic Publication: PDF
Abstract:

The ECRYPT/eSTREAM organisers have required all submissions to be benchmarked against the Advanced Encryption Standard (AES) and where applicable, a secure trusted authentication mechanism. The goal is stated to be to identify those eSTREAM submissions that offer an advance over AES efficiency in any one or more benchmark dimensions.

In this paper, we respond to the eSTREAM requirement and offer a wide-sweeping multi-dimensional analysis and comparison between VEST and the hardware implementations of the AES, AES-HMAC and SHA-2 primitives.

This analysis clearly establishes VEST superiority over the AES, HMAC and SHA-2 primitives generally while direct comparisons between VEST and several of the best AES HMAC and SHA-2 implementations illustrates VEST superiority measuring in the hundreds of percent on several design dimensions or axis.
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Citation:

Benjamin Gittins, Howard A. Landman, Sean O'Neil, Ron Kelson, "A Presentation on VEST Hardware Performance, Chip Area Measurements, Power Consumption Estimates and Benchmarking in Relation to the AES, SHA-256 and SHA-512", Synaptic Laboratories Limited, 2005.
Related work: pub: 20 Gb/s VEST-32 on 110nm LSI Rapidchip (2006)


Last Updated on Sunday, 23 October 2011 09:01